1. Field of the Invention
This invention is related to the field of integrated circuits, and more particularly, to sharing a debug port among the cores of multi-core integrated circuits.
2. Description of the Related Art
Realizing the importance of emulation techniques in both hardware and software development, most manufacturers of microprocessors and DSP's now incorporate debug and/or testing interfaces into their designs. For instance, a processor emulator may be incorporated into the processor itself. The list of debug interface enabled CPU's includes members of the Intel Pentium processor family, Motorola and IBM PowerPC processor families, as well as AMD, MIPS, ARM and SPARC processor families. The IEEE organization has also published a standard (IEEE-ISTO 5001) for debug interfaces. The various manufacturers may use different names for their debug interfaces, including BDM Port, (hardware debug tool) HDT Port and COP port, but the basic functionality may be quite similar among most implementations.
Access to the testing functions is typically provided via a JTAG compliant port supplemented by 2 or 3 additional special purpose signals. Processor designers may extend the JTAG instruction set to include vendor-specific instructions for controlling the processor core. Low-level debug functions typically include: stop the processor; read/write memory locations; read/write I/O locations; set/remove breakpoints; single step code execution; and code tracing.
As integrated circuits, such as processors, gain complexity multiple logic cores may be included in a single integrated circuit. For instance, a dual-core processor may include two individual logic cores and processors with four or more individual logic cores are common. However, a multi-core integrated circuit, such as a dual-core processor, may only include a single debug port or interface to test the integrated circuit including the logic cores. Traditionally, a single, shared debug port, such as a JTAG interface cannot be used to individually test or debug the logic cores of a multi-core integrated circuit.